Datasheet

Processor Integrated I/O (IIO) Configuration Registers
40 Datasheet, Volume 2
3.2.3 IIO PCI Express* Configuration Space Registers
Table 3-1. (DMI2 Mode) Legacy Configuration Map – Device 0 Function 0 – 
Offset 00h–0FCh
DID VID 0h 80h
PCISTS PCICMD 4h
84h
CCR RID 8h
88h
BIST HDR PLAT CLSR Ch
8Ch
10h PXPCAP PXPNXTPTR PXPCAPID 90h
14h DEVCAP 94h
18h 98h
1Ch 9Ch
20h A0h
24h A4h
28h A8h
SDID SVID 2Ch
ROOTCON ACh
30h B0h
CAPPTR 34h DEVCAP2 B4h
38h B8h
INTPIN INTL 3Ch LNKCAP2 BCh
40h C0h
44h C4h
48h C8h
4Ch CCh
DMIRCBAR 50h
D0h
54h D4h
58h D8h
5Ch DCh
60h PMCAP E0h
64h PMCSR E4h
68h E8h
6Ch ECh
70h DEVSTS DEVCTRL
DEV
STS
74h
78h DEVCTRL2
7Ch