Datasheet

Datasheet, Volume 2 397

Processor Uncore Configuration Registers
4.2.12.34 RIRILV7OFFSET_3—RIR Range Rank Interleave 7 
OFFSET Register
4.2.12.35 RIRILV0OFFSET_4—RIR Range Rank Interleave 0 
OFFSET Register
RIRILV7OFFSET_3
Bus: 1 Device: 15 Function: 2 Offset: 19Ch
Bus: 1 Device: 15 Function: 3 Offset: 19Ch
Bus: 1 Device: 15 Function: 4 Offset: 19Ch
Bus: 1 Device: 15 Function: 5 Offset: 19Ch
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT7
Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET7
RIR[5:0].RANKOFFSET7[38:26] == rank interleave 0 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved
RIRILV0OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1A0h
Bus: 1 Device: 15 Function: 3 Offset: 19Ch
Bus: 1 Device: 15 Function: 4 Offset: 19Ch
Bus: 1 Device: 15 Function: 5 Offset: 19Ch
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT0
Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET0
RIR[5:0].RANKOFFSET0[38:26] == rank interleave 0 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved