Datasheet

Datasheet, Volume 2 395
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Processor Uncore Configuration Registers
4.2.12.30 RIRILV3OFFSET_3—RIR Range Rank Interleave 3 
OFFSET Register
4.2.12.31 RIRILV4OFFSET_3—RIR Range Rank Interleave 4 
OFFSET Register
RIRILV3OFFSET_3
Bus: 1 Device: 15 Function: 2 Offset: 18Ch
Bus: 1 Device: 15 Function: 3 Offset: 18Ch
Bus: 1 Device: 15 Function: 4 Offset: 18Ch
Bus: 1 Device: 15 Function: 5 Offset: 18Ch
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT3
Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET3
RIR[5:0].RANKOFFSET3[38:26] == rank interleave 3 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved
RIRILV4OFFSET_3
Bus: 1 Device: 15 Function: 2 Offset: 190h
Bus: 1 Device: 15 Function: 3 Offset: 190h
Bus: 1 Device: 15 Function: 4 Offset: 190h
Bus: 1 Device: 15 Function: 5 Offset: 190h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT4
Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET4
RIR[5:0].RANKOFFSET4[38:26] == rank interleave 4 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved