Datasheet

Datasheet, Volume 2 39
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Processor Integrated I/O (IIO) Configuration Registers
Figure 3-2 illustrates how each PCI Express/DMI2 port’s configuration space appears to
software. Each PCI Express configuration space has three regions:
• Standard PCI Header: This region is the standard PCI-to-PCI bridge header
providing legacy OS compatibility and resource management.
• PCI Device Dependent Region: This region is also part of standard PCI
configuration space and contains basic PCI capability structures and other port
specific registers. For the processor, the supported capabilities are:
— SVID/SDID Capability
— Message Signalled Interrupts
— Power Management
— PCI Express Capability
• PCI Express Extended Configuration Space: This space is an enhancement
beyond standard PCI and only accessible with PCI Express aware software.
Figure 3-2. Device 1/Functions 0–1 (Root Ports) – Device 2/Function 0–3 (Root Port
Mode) and Devices 3/Functions 0–3 (Root Ports) Type 1 Configuration Space
0x00
0x40
0x100
0xFFF
ACS
Capability
MSI Capability
P2 P Header
CAP_ PTR
PCIe Capability
Extended
Configuration Space
PCI Device
Dependent
PCI Header
PM Capability
SVID / SDID Capability
VSEC
-
REUT
Capability
AER Capability
Confi gur ation Space
Legacy