Datasheet

Datasheet, Volume 2 387

Processor Uncore Configuration Registers
4.2.12.15 RIRILV4OFFSET_1—RIR Range Rank Interleave 4 
OFFSET Register
4.2.12.16 RIRILV5OFFSET_1—RIR Range Rank Interleave 5 
OFFSET Register
RIRILV4OFFSET_1
Bus: 1 Device: 15 Function: 2 Offset: 150h
Bus: 1 Device: 15 Function: 3 Offset: 150h
Bus: 1 Device: 15 Function: 4 Offset: 150h
Bus: 1 Device: 15 Function: 5 Offset: 150h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT4
Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET4
RIR[5:0].RANKOFFSET4[38:26] == rank interleave 4 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved
RIRILV5OFFSET_1
Bus: 1 Device: 15 Function: 2 Offset: 154h
Bus: 1 Device: 15 Function: 3 Offset: 154h
Bus: 1 Device: 15 Function: 4 Offset: 154h
Bus: 1 Device: 15 Function: 5 Offset: 154h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RIR_RNK_TGT5
Target rank ID for rank interleave 5 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW-LB 0h
RIR_OFFSET5
RIR[5:0].RANKOFFSET5[38:26] == rank interleave 5 offset, 64 MB granularity
(processor’s minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved