Datasheet

Processor Uncore Configuration Registers
380 Datasheet, Volume 2
4.2.12 Integrated Memory Controller Error Injection Registers
Complete address match (Addr[45:3]) and mask is supported for all Home Agent
writes. Error injection does not use the response logic triggers and uses the match
mask logic output to determine which writes need to get error injection. Users can
program up to two x4 device masks (8-bits per chunk - 64 bits per cacheline).
4.2.12.1 PXPENHCAP—PCI Express* Capability Register
This field points to the next Capability in extended configuration space.
4.2.12.2 RIRWAYNESSLIMIT_[0:4]—RIR Range Wayness and 
Limit Register
There are total of 5 RIR ranges (represents how many rank interleave ranges supported
to cover customer DIMM configuration.).
PXPENHCAP
Bus: 1 Device: 15 Function: 2 Offset: 100h
Bus: 1 Device: 15 Function: 3 Offset: 100h
Bus: 1 Device: 15 Function: 4 Offset: 100h
Bus: 1 Device: 15 Function: 5 Offset: 100h
Bit Attr
Reset
Value
Description
31:20 RO 000h Next Capability Offset
RIRWAYNESSLIMIT_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 108h, 10Ch, 110h, 114h, 118h
Bus: 1 Device: 15 Function: 3 Offset: 108h, 10Ch, 110h, 114h, 118
Bus: 1 Device: 15 Function: 4 Offset: 108h, 10Ch, 110h, 114h, 118h
Bus: 1 Device: 15 Function: 5 Offset: 108h, 10Ch, 110h, 114h, 118h
Bit Attr
Reset
Value
Description
31 RW-LB 0b
RIR_VAL
Range Valid when set; otherwise, invalid
30 RV 0h Reserved
29:28 RW-LB 0h
RIR_WAY
rank interleave wayness
00 = 1 way
01 = 2 way
10 = 4 way
11 = 8 way
27:11 RV 0h Reserved
10:1 RW-LB 0h
RIR_LIMIT
RIR[5:0].LIMIT[38:29] == highest address of the range in channel address space,
192 GB in independent channel, 512 MB granularity. M= How many rank
interleave ranges supported to cover customer DIMM configuration. In the
processor M=6.
0RV0hReserved