Datasheet

Datasheet, Volume 2 379
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Processor Uncore Configuration Registers
4.2.11.40 RIRILV6OFFSET_4—RIR Range Rank Interleave 6 
OFFSET Register
4.2.11.41 RIRILV7OFFSET_4—RIR Range Rank Interleave 7 
OFFSET Register
RIRILV6OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1B8h
Bus: 1 Device: 15 Function: 3 Offset: 1B8h
Bus: 1 Device: 15 Function: 4 Offset: 1B8h
Bus: 1 Device: 15 Function: 5 Offset: 1B8h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT6
Target rank ID for rank interleave 6 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET6
RIR[5:0].RANKOFFSET6[38:26] == rank interleave 6 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved
RIRILV7OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1BCh
Bus: 1 Device: 15 Function: 3 Offset: 1BCh
Bus: 1 Device: 15 Function: 4 Offset: 1BCh
Bus: 1 Device: 15 Function: 5 Offset: 1BCh
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT7
Target rank ID for rank interleave 7 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET7
RIR[5:0].RANKOFFSET7[38:26] == rank interleave 0 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved