Datasheet

Datasheet, Volume 2 377

Processor Uncore Configuration Registers
4.2.11.36 RIRILV2OFFSET_4—RIR Range Rank Interleave 2 
OFFSET Register
4.2.11.37 RIRILV3OFFSET_4—RIR Range Rank Interleave 3 
OFFSET Register
RIRILV2OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1A8h
Bus: 1 Device: 15 Function: 3 Offset: 1A8h
Bus: 1 Device: 15 Function: 4 Offset: 1A8h
Bus: 1 Device: 15 Function: 5 Offset: 1A8h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT2
Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET2
RIR[5:0].RANKOFFSET2[38:26] == rank interleave 2 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved
RIRILV3OFFSET_4
Bus: 1 Device: 15 Function: 2 Offset: 1ACh
Bus: 1 Device: 15 Function: 3 Offset: 1ACh
Bus: 1 Device: 15 Function: 4 Offset: 1ACh
Bus: 1 Device: 15 Function: 5 Offset: 1ACh
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT3
Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET3
RIR[5:0].RANKOFFSET3[38:26] == rank interleave 3 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved