Datasheet

Datasheet, Volume 2 37
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Processor Integrated I/O (IIO) Configuration Registers
3 Processor Integrated I/O (IIO)
Configuration Registers
3.1 Processor IIO Devices (PCI Bus CPUBUSNO (0))
The processor IIO contains 10 PCI devices within a single, physical component. The
configuration registers for the devices are mapped as devices residing on PCI Bus
“CPUBUSNO(0)” where CPUBUSNO(0) is programmable by BIOS.
3.2 PCI Configuration Space Registers (CSRs)
This section covers registers which reside in legacy PCIe configuration space.
Comments at the top of the table indicate what devices/functions the description
applies to. Exceptions that apply to specific functions are noted in the individual bit
descriptions.
3.2.1 Unimplemented Devices/Functions and Registers
Configuration reads to unimplemented functions and devices will return all ones
emulating a master abort response. Note that there is no asynchronous error reporting
that happens when a configuration read master aborts. Configuration writes to
unimplemented functions and devices will return a normal response.
Software should not attempt or rely on reads or writes to unimplemented registers or
register bits. Unimplemented registers should return 00h bytes. Writes to
unimplemented registers are ignored. For configuration writes to these register (require
a completion), the completion is returned with a normal completion status (not master-
aborted).
3.2.2 PCI Bus Number
In the following tables, the PCI Bus numbers are all marked as “bus 0”. The specific bus
number for all PCIe devices in the processor is specified in the CPUBUSNO register
found at Section 3.3.3.14, “CPUBUSNO—CPU Internal Bus Numbers Register” on
page 165.