Datasheet

Processor Uncore Configuration Registers
362 Datasheet, Volume 2
4.2.11.5 RIRILV3OFFSET_[0:4]—RIR Range Rank Interleave 3 
OFFSET Register
4.2.11.6 RIRILV4OFFSET_[0:4]—RIR Range Rank Interleave 4 
OFFSET Register
4.2.11.7 RIRILV5OFFSET_[0:4]—RIR Range Rank Interleave 5 
OFFSET Register
RIRILV3OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 12Ch
Bus: 1 Device: 15 Function: 3 Offset: 12Ch
Bus: 1 Device: 15 Function: 4 Offset: 12Ch
Bus: 1 Device: 15 Function: 5 Offset: 12Ch
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT3
Target rank ID for rank interleave 3 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET3
RIR[5:0].RANKOFFSET3[38:26] == rank interleave 3 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved
RIRILV4OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 130h
Bus: 1 Device: 15 Function: 3 Offset: 130h
Bus: 1 Device: 15 Function: 4 Offset: 130h
Bus: 1 Device: 15 Function: 5 Offset: 130h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT4
Target rank ID for rank interleave 4 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET4
RIR[5:0].RANKOFFSET4[38:26] == rank interleave 4 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)
1:0 RV 0h Reserved
RIRILV5OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 134h
Bus: 1 Device: 15 Function: 3 Offset: 134h
Bus: 1 Device: 15 Function: 4 Offset: 134h
Bus: 1 Device: 15 Function: 5 Offset: 134h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT5
Target rank ID for rank interleave 5 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET5
RIR[5:0].RANKOFFSET5[38:26] == rank interleave 5 offset, 64 MB granularity
(processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-way
interleave.)