Datasheet

Datasheet, Volume 2 361
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Processor Uncore Configuration Registers
4.2.11.3 RIRILV1OFFSET_[0:4]—RIR Range Rank Interleave 1 
OFFSET Register
4.2.11.4 RIRILV2OFFSET_[0:4]—RIR Range Rank Interleave 2 
OFFSET Register
RIRILV1OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 124h
Bus: 1 Device: 15 Function: 3 Offset: 124h
Bus: 1 Device: 15 Function: 4 Offset: 124h
Bus: 1 Device: 15 Function: 5 Offset: 124h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT1
Target rank ID for rank interleave 1 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET1
RIR[5:0].RANKOFFSET1[38:26] == rank interleave 1 offset, 64 MB granularity
(the processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved
RIRILV2OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 128h
Bus: 1 Device: 15 Function: 3 Offset: 128h
Bus: 1 Device: 15 Function: 4 Offset: 128h
Bus: 1 Device: 15 Function: 5 Offset: 128h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT2
Target rank ID for rank interleave 2 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET2
RIR[5:0].RANKOFFSET2[38:26] == rank interleave 2 offset, 64 MB granularity
(the processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved