Datasheet

Processor Uncore Configuration Registers
360 Datasheet, Volume 2
4.2.11 Integrated Memory Controller Channel Rank Registers
There are a total of 6 RIR ranges (represents how many rank interleave ranges
supported to cover DIMM configuration).
4.2.11.1 RIRWAYNESSLIMIT_[0:4]—RIR Range Wayness and 
Limit Register
4.2.11.2 RIRILV0OFFSET_[0:4]—RIR Range Rank Interleave 0 
OFFSET Register
RIRWAYNESSLIMIT_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 108h, 10Ch, 110h, 114h, 118h
Bus: 1 Device: 15 Function: 3 Offset: 108h, 10Ch, 110h, 114h, 118h
Bus: 1 Device: 15 Function: 4 Offset: 108h, 10Ch, 110h, 114h, 118h
Bus: 1 Device: 15 Function: 5 Offset: 108h, 10Ch, 110h, 114h, 118h
Bit Attr
Reset
Value
Description
31 RW 0b
RIR_VAL
Range Valid when set; otherwise, invalid
30 RV 0h Reserved
29:28 RW 0h
RIR_WAY
rank interleave wayness
00 = 1 way,
01 = 2 way,
10 = 4 way,
11 = 8 way.
27:11 RV 0h Reserved
10:1 RW 0h
RIR_LIMIT
RIR[5:0].LIMIT[38:29] == highest address of the range in channel address space,
384 GB in lock-step/192 GB in independent channel, 512 MB granularity. M= How
many rank interleave ranges supported to cover customer DIMM configuration. In
the processor M=6.
0RV0hReserved
RIRILV0OFFSET_[0:4]
Bus: 1 Device: 15 Function: 2 Offset: 120h
Bus: 1 Device: 15 Function: 3 Offset: 120h
Bus: 1 Device: 15 Function: 4 Offset: 120h
Bus: 1 Device: 15 Function: 5 Offset: 120h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW 0h
RIR_RNK_TGT0
Target rank ID for rank interleave 0 (used for 1/2/4/8-way RIR interleaving).
15 RV 0h Reserved
14:2 RW 0h
RIR_OFFSET0
RIR[5:0].RANKOFFSET0[38:26] == rank interleave 0 offset, 64 MB granularity
(the processor minimum rank size is 512 MB. 512 MB/8 interleave = 64 MB per 8-
way interleave.)
1:0 RV 0h Reserved