Datasheet

Datasheet, Volume 2 359
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Processor Uncore Configuration Registers
4.2.10 Integrated Memory Controller Memory Target Address
Decoder Registers
4.2.10.1 TADCHNILVOFFSET_[0:11]—TAD Range Channel Interleave i 
OFFSET Register
TADCHNILVOFFSET_[0:11]
Bus: 1 Device: 15 Function: 2 Offset: 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh
Bus: 1 Device: 15 Function: 2 Offset: B0h, B4h, B8h, BCh
Bus: 1 Device: 15 Function: 3 Offset: 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh
Bus: 1 Device: 15 Function: 3 Offset: B0h, B4h, B8h, BCh
Bus: 1 Device: 15 Function: 4 Offset: 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh
Bus: 1 Device: 15 Function: 4 Offset: B0h, B4h, B8h, BCh
Bus: 1 Device: 15 Function: 5 Offset: 90h, 94h, 98h, 9Ch, A0h, A4h, A8h, ACh
Bus: 1 Device: 15 Function: 5 Offset: B0h, B4h, B8h, BCh
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:28 RW-LB 0h
CHN_IDX_OFFSET: Reverse Address Translation Channel Index Offset
BIOS programs this field by calculating:
(TAD[N].BASE / TAD[N].TAD_SKT_WAY) % TAD[N].TAD_CH_WAY
where % is the modulo function.
CHN_IDX_OFFSET can have a value of 0, 1, or 2.
In this equation, the BASE is the lowest address in the TAD range. The
TAD_SKT_WAY is 1, 2, 4, or 8, and TAD_CH_WAY is 1, 2, 3, or 4. CHN_IDX_OFFSET
will always end up being zero if TAD_CH_WAY is not equal to 3. If TAD_CH_WAY is 3,
CHN_IDX_OFFSET can be 0, 1, or 2.
27:26 RV 0h Reserved
25:6 RW-LB 0h
TAD_OFFSET
Channel interleave 0 offset; that is, CHANNELOFFSET[45:26] == channel interleave
i offset, 64 MB granularity .
5:0 RV 0h Reserved