Datasheet

Processor Uncore Configuration Registers
358 Datasheet, Volume 2
4.2.9.2 DIMMMTR_[0:2]—DIMM Memory Technology Register
DIMMMTR_[0:2]
Bus: 1 Device: 15 Function: 2 Offset: 80h, 84h, 88h
Bus: 1 Device: 15 Function: 3 Offset: 80h, 84h, 88h
Bus: 1 Device: 15 Function: 4 Offset: 80h, 84h, 88h
Bus: 1 Device: 15 Function: 5 Offset: 80h, 84h, 88h
Bit Attr
Reset
Value
Description
31:20 RV 0h Reserved
19:16 RW-LB 0h
RANK_DISABLE Control
RANK Disable Control to disable patrol, refresh, and ZQCAL operation. This bit
setting must be set consistently with TERM_RNK_MSK; that is, both corresponding
bits cannot be set at the same time. Thus, a disabled rank must not be selected
for the termination rank.
RANK_DISABLE[3]; that is, bit 19: rank 3 disable.
Note: DIMMMTR_2.RANK_DISABLE[3] is don’t care since DIMM 2 must not be
quad-rank.
RANK_DISABLE[2]; that is, bit 18: rank 2 disable.
Note: DIMMMTR_2.RANK_DISABLE[2] is don’t care since DIMM 2 must not be
quad-rank.
RANK_DISABLE[1]; that is, bit 17: rank 1 disable
RANK_DISABLE[0]; that is, bit 16: rank 0 disable
When set, no patrol or refresh will be perform on this rank. ODT termination is not
affected by this bit.
15 RV 0h Reserved
14 RW-LB 0h
DIMM_POP
DIMM populated if set; otherwise, unpopulated.
13:12 RW-LB 0h
RANK_CNT
00 = SR
01 = DR
10 = QR
11 = reserved
11:9 RV 0h Reserved
4:2 RW-LB 0h
RA_WIDTH
000 = reserved (the processor does not support 512Mb DDR3)
001 = 13 bits
010 = 14 bits
011 = 15 bits
100 = 16 bits
101 = 17 bits
110 = 18 bits
111 = reserved
1:0 RW-LB 0h
CA_WIDTH
00 = 10 bits
01 = 11 bits
10 = 12 bits
11 = reserved