Datasheet

Processor Uncore Configuration Registers
356 Datasheet, Volume 2
4.2.8.9 SMB_PERIOD_CFG—SMBus Clock Period Config Register
4.2.8.10 SMB_PERIOD_CNTR—SMBus Clock Period Counter Register
4.2.8.11 SMB_TSOD_POLL_RATE—SMBus TSOD POLL RATE Register
SMB_PERIOD_CFG
Bus: 1 Device: 15 Function: 0 Offset: 1A0h
Bit Attr
Reset
Value
Description
15:0 RWS 0FA0h
SMB_CLK_PRD
This field specifies both SMBus Clock in number of DCLK.
Note: To generate a 50% duty cycle SCL, half of the SMB_CLK_PRD is used to
generate SCL high. SCL must stay low for at least another half of the
SMB_CLK_PRD before pulling high. It is recommend to program an even value in
this field since the hardware is simply doing a right shift for the divided by 2
operation.
Note: The 100KHz SMB_CLK_PRD default value is calculated based on 800MT/s
(400MHz) DCLK.
SMB_PERIOD_CNTR
Bus: 1 Device: 15 Function: 0 Offset: 1A4h
Bit Attr
Reset
Value
Description
31:16 RO-V 0000h
SMB1_CLK_PRD_CNTR
SMBus #1 Clock Period Counter for Ch 23This field is the current SMBus Clock
Period Counter Value.
15:0 RO-V 0000h
SMB0_CLK_PRD_CNTR
SMBus #0 Clock Period Counter for Ch 01This field is the current SMBus Clock
Period Counter Value.
SMB_TSOD_POLL_RATE
Bus: 1 Device: 15 Function: 0 Offset: 1A8h
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17:0 RWS 3E800h
SMB_TSOD_POLL_RATE
TSOD poll rate configuration between consecutive TSOD accesses to the TSOD
devices on the same SMBus segment. This field specifies the TSOD poll rate in
number of 500 ns per CNFG_500_NANOSEC register field definition.