Datasheet

Datasheet, Volume 2 355
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Processor Uncore Configuration Registers
4.2.8.8 SMB_TSOD_POLL_RATE_CNTR_1—SMBus Clock Period 
Counter Register
10 RW 0h
SMB_SOFT_RST
SMBus software reset strobe to graceful terminate pending transaction (after
ACK) and keep the SMB from issuing any transaction until this bit is cleared. If
slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0
(for more than 35ms) to force hung the SMB slaves to time-out and put it in idle
state without using power good reset or warm reset.
Note: software need to set the SMB_CKOVRD back to 1 after 35 ms in order to
force slave devices to time-out in case there is any pending transaction. The
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was
such pending transaction time-out (non-graceful termination). If the pending
transaction was a write operation, the slave device content may be corrupted by
this clock override operation. A subsequent SMB command will automatically
cleared the SMB_SBE.
9RV0hReserved
8RW-LB 0h
SMB_TSOD_POLL_EN: TSOD Ppolling Enable
0 = Disable TSOD polling and enable SPDCMD accesses.
1 = Disable SPDCMD access and enable TSOD polling.
It is important to make sure no pending SMBus transaction and the TSOD polling
must be disabled (and pending TSOD polling must be drained) before changing
the TSODPOLLEN.
7:0 RW-LB 00h
TSOD_PRESENT for the lower and upper channels
DIMM slot mask to indicate whether the DIMM is equipped with TSOD sensor.
Bit 7: must be programmed to zero. Upper channel slot #3 is not supported
Bit 6: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #2
Bit 5: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #1
Bit 4: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #0
Bit 3: must be programmed to zero. Lower channel slot #3 is not supported
Bit 2: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #2
Bit 1: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #1
Bit 0: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #0
SMB_TSOD_POLL_RATE_CNTR_1
Bus: 1 Device: 15 Function: 0 Offset: 19Ch
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17:0 RW-LV 00000h
SMB_TSOD_POLL_RATE_CNTR: TSOD Poll Rate Counter
When counter is decremented to zero – reset to zero or written to zero –
SMB_TSOD_POLL_RATE value is loaded into this counter and appear the updated
value in the next DCLK.
SMBCntl_1
Bus: 1 Device: 15 Function: 0 Offset: 198h
Bit Attr
Reset
Value
Description