Datasheet

Processor Uncore Configuration Registers
352 Datasheet, Volume 2
4.2.8.5 SMB_STAT_1—SMBus Status Register
This register provides the interface to the SMBus/I
2
C (SCL and SDA signals) that is
used to access the Serial Presence Detect EEPROM or Thermal Sensor on DIMM (TSOD)
that defines the technology, configuration, and speed of the DIMMs controlled by iMC.
SMB_STAT_1
Bus: 1 Device: 15 Function: 0 Offset: 190h
Bit Attr
Reset
Value
Description
31 RO-V 0h
SMB_RDO: Read Data Valid
This bit is set by iMC when the Data field of this register receives read data from
the SPD/TSOD after completion of an SMBus read command. It is cleared by iMC
when a subsequent SMBus read command is issued.
30 RO-V 0h
SMB_WOD: Write Operation Done
This bit is set by iMC when a SMBus Write command has been completed on the
SMBus. It is cleared by iMC when a subsequent SMBus Write command is issued.
29 RO-V 0h
SMB_SBE: SMBus Error
This bit is set by iMC if an SMBus transaction (including the TSOD polling or
message channel initiated SMBus access) that does not complete successfully
(non-Ack has been received from slave at expected Ack slot of the transfer). If a
slave device is asserting clock stretching, IMC does not have logic to detect this
condition to set the SBE bit directly; however, the SMBus master will detect the
error at the corresponding transaction’s expected ACK slot.
This bit is cleared by iMC when an SMBus read/write command is issued or by
setting the SMBSoftRst.
28 ROS-V 0h
SMB_BUSY: SMBus Busy state
This bit is set by iMC while an SMBus/I
2
C command (including TSOD command
issued from IMC hardware) is executing. Any transaction that is completed
normally or gracefully will clear this bit automatically. By setting the
SMB_SOFT_RST will also clear this bit.
This register bit is sticky across reset so any surprise reset during pending SMBus
operation will sustain the bit assertion across surprised warm-reset. BIOS reset
handler can read this bit before issuing any SMBus transaction to determine
whether a slave device may need special care to force the slave to idle state (such
as, using clock override toggling (SMB_CKOVRD) and/or using induced time-out
by asserting SMB_CKOVRD for 25-35ms).
27 RV 0h Reserved
26:24 RO-V 111b
Last Issued TSOD Slave Address
This field captures the last issued TSOD slave address. Here is the slave address
and the DDR CHN and DIMM slot mapping:
Slave Address: 0 -- Channel: Even Chn; Slot #: 0
Slave Address: 1 -- Channel: Even Chn; Slot #: 1
Slave Address: 2 -- Channel: Even Chn; Slot #: 2
Slave Address: 3 -- Channel: Even Chn; Slot #: 3 (reserved for future use)
Slave Address: 4 -- Channel: Odd Chn; Slot #: 0
Slave Address: 5 -- Channel: Odd Chn; Slot #: 1
Slave Address: 6 -- Channel: Odd Chn; Slot #: 2
Slave Address: 7 -- Channel: Odd Chn; Slot #: 3 (reserved for future use)
Since this field only captures the TSOD polling slave address. During SMB error
handling, software should check the hung SMB_TSOD_POLL_EN state before
disabling the SMB_TSOD_POLL_EN in order to qualify whether this field is valid.
23:16 RV 0h Reserved