Datasheet

Datasheet, Volume 2 351
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Processor Uncore Configuration Registers
4.2.8.4 SMB_TSOD_POLL_RATE_CNTR_[0:1]—SMBus Clock Period 
Counter Register
8RW-LB 0h
SMB_TSOD_POLL_EN: TSOD Polling Enable
0 = Disable TSOD polling and enable SPDCMD accesses.
1 = Disable SPDCMD access and enable TSOD polling.
It is important to make sure no pending SMBus transaction and the TSOD polling
must be disabled (and pending TSOD polling must be drained) before changing
the TSODPOLLEN.
7:0 RW-LB 00h
TSOD_PRESENT for the lower and upper channels
DIMM slot mask to indicate whether the DIMM is equipped with TSOD sensor.
Bit 7: must be programmed to zero. Upper channel slot #3 is not supported
Bit 6: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #2
Bit 5: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #1
Bit 4: TSOD PRESENT at upper channel (ch 1 or ch 3) slot #0
Bit 3: must be programmed to zero. Lower channel slot #3 is not supported
Bit 2: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #2
Bit 1: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #1
Bit 0: TSOD PRESENT at lower channel (ch 0 or ch 2) slot #0
SMB_TSOD_POLL_RATE_CNTR_[0:1]
Bus: 1 Device: 15 Function: 0 Offset: 18Ch
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17:0 RW-LV 00000h
SMB_TSOD_POLL_RATE_CNTR: TSOD Poll Rate Counter
When counter is decremented to zero – reset to zero or written to zero –
SMB_TSOD_POLL_RATE value is loaded into this counter and appear the updated
value in the next DCLK.
SMBCntl_[0:1]
Bus: 1 Device: 15 Function: 0 Offset: 188h
Bit Attr
Reset
Value
Description