Datasheet

Processor Uncore Configuration Registers
350 Datasheet, Volume 2
4.2.8.3 SMBCntl_[0:1]—SMBus Control Register
SMBCntl_[0:1]
Bus: 1 Device: 15 Function: 0 Offset: 188h
Bit Attr
Reset
Value
Description
31:28 RWS 1010b
SMB_DTI: Device Type Identifier
This field specifies the device type identifier. Only devices with this device-type will
respond to commands.
0011 = Specifies TSOD.
1010 = Specifies EEPROMs.
0110 = Specifies a write-protect operation for an EEPROM.
Other identifiers can be specified to target non-EEPROM devices on the SMBus.
Note: IMC based hardware TSOD polling uses hardcoded DTI. Changing this field
has no effect on the hardware based TSOD polling.
27 RWS-V 1h
SMB_CKOVRD: Clock Override
0 = Clock signal is driven low, overriding writing a ’1’ to CMD.
1 = Clock signal is released high, allowing normal operation of CMD.
Toggling this bit can be used to ’budge’ the port out of a ’stuck’ state.
Software can write this bit to 0 and the SMB_SOFT_RST to 1 to force hung SMBus
controller and the SMB slaves to idle state without using power good reset or
warm reset.
Note: software need to set the SMB_CKOVRD back to 1 after 35 ms in order to
force slave devices to time-out in case there is any pending transaction. The
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was
such pending transaction time-out (non-graceful termination). If the pending
transaction was a write operation, the slave device content may be corrupted by
this clock override operation. A subsequent SMB command will automatically clear
the SMB_SBE.
Note: iMC added SMBus time-out control timer in ES2. When the time-out control
timer expires, the SMB_CKOVRD# will "de-assert"; that is, return to 1 value and
clear the SMB_SBE=0.
26 RW-O 0h
SMB_DIS_WRT: Disable SMBus Write
Writing a 0 to this bit enables CMD to be set to 1; Writing a 1 to force CMD bit to
be always 0; that is, disabling SMBus write. This bit can only be written 0/1 once
to enable SMB write disable feature. SMBus Read is not affected. The I
2
C Write
Pointer Update Command is not affected.
Important Note to BIOS: Since BIOS is the source to update SMBCNTL_x
register initially after reset, it is important to determine whether the SMBus can
have write capability before writing any upper bits (bit 24:31) using byte-enable
config write (or writing any bit within this register using 32b config write) within
the SMBCNTL register.
25:24 RV 0h Reserved
20:11 RV 0h Reserved
10 RW 0h
SMB_SOFT_RST
SMBus software reset strobe to graceful terminate pending transaction (after
ACK) and keep the SMB from issuing any transaction until this bit is cleared. If
slave device is hung, software can write this bit to 1 and the SMB_CKOVRD to 0
(for more than 35 ms) to force hung the SMB slaves to time-out and put it in idle
state without using power good reset or warm reset.
Note: Software needs to set the SMB_CKOVRD back to 1 after 35 ms in order to
force slave devices to time-out in case there is any pending transaction. The
corresponding SMB_STAT_x.SMB_SBE error status bit may be set if there was
such pending transaction time-out (non-graceful termination). If the pending
transaction was a write operation, the slave device content may be corrupted by
this clock override operation. A subsequent SMB command will automatically
cleared the SMB_SBE.
9RV0hReserved