Datasheet

Datasheet, Volume 2 35
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Configuration Process and Registers
2.3 Configuration Mechanisms
The processor is the originator of configuration cycles. Internal to the processor,
transactions received through both of the below configuration mechanisms are
translated to the same format.
2.3.1 Standard PCI Express* Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration
cycles.
The PCI specification defines a slot based "configuration space" that allows each device
to contain up to eight functions, with each function containing up to 256, 8-bit
configuration registers. The PCI specification defines two bus cycles to access the PCI
configuration space—Configuration Read and Configuration Write. Memory and I/O
spaces are supported directly by the processor. Configuration space is supported by a
mapping mechanism implemented within the processor.
2.4 Device Mapping
Each component in the processor is uniquely identified by a PCI bus address consisting
of Bus Number, Device Number and Function Number. Device configuration is based on
the PCI Type 0 configuration conventions. All processor registers appear on the PCI bus
assigned for the processor socket.
Table 2-1. Functions Specifically Handled by the Processor (Sheet 1 of 2)
Register Group DID Device Function Comment
DMI2 3C00h 0 0 x4 Link from Processor to PCH
PCI Express Root Port 1
3C02h,
3C03h
1 0–1 x8 or x4 max link width
PCI Express Root Port 2
3C04h,
3C05h,
3C06h,
3C07h
2 0–3 x16, x8 or x4 max link width
PCI Express Root Port 3
3C08h,
3C09h,
3COAh,
3C0Bh
3 0–3 x16, x8 or x4 max link width
Core 3C28h 5 0
Address Map, VTd_Misc, System
Management
Core 3C2Ah 5 2 RAS, Control Status and Global Errors
Core 3C2Ch 5 4 I/O APIC
Core 3C40h 5 6 IIO Switch and IRP Perfmon
PCU
3CC0h,
3CC1h,
3CC2h
3CD0h
10 0–3 Power Control Unit
UBOX 3CE0h 11 0 Scratchpad and Semaphores
UBOX 3CE3h 11 3 Scratchpad and Semaphores
Caching Agent (CBo)
3CE8h,
3CEAh,
3CECh,
3CEEh
12 0–3 Unicast Registers