Datasheet

Datasheet, Volume 2 347
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Processor Uncore Configuration Registers
4.2.7.7 MH_EXT_STAT Register
Capture externally asserted MEM_HOT[1:0]# assertion detection.
4.2.8 Integrated Memory Controller SMBus Registers
4.2.8.1 SMB_STAT_[0:1]—SMBus Status Register
This register provides the interface to the SMBus/I
2
C (SCL and SDA signals) that is
used to access the Serial Presence Detect EEPROM or Thermal Sensor on DIMM (TSOD)
that defines the technology, configuration, and speed of the DIMM's controlled by iMC.
MH_EXT_STAT
Bus: 1 Device: 15 Function: 0 Offset: 124h
Bit Attr
Reset
Value
Description
31:2 RV 0h Reserved
1RW1C0b
MH_EXT_STAT_1
MEM_HOT[1]# assertion status at this sense period.
Set if MEM_HOT[1]# is asserted externally for this sense period. This running
status bit will automatically update with the next sensed value in the next
MEM_HOT input sense phase.
0RW1C0b
MH_EXT_STAT_0
MEM_HOT[0]# assertion status at this sense period.
Set if MEM_HOT[0]# is asserted externally for this sense period. This running
status bit will automatically update with the next sensed value in the next
MEM_HOT input sense phase.
SMB_STAT_[0:1]
Bus: 1 Device: 15 Function: 0 Offset: 180h
Bit Attr
Reset
Value
Description
31 RO-V 0h
SMB_RDO
Read Data Valid
This bit is set by iMC when the Data field of this register receives read data from
the SPD/TSOD after completion of an SMBus read command. It is cleared by iMC
when a subsequent SMBus read command is issued.
30 RO-V 0h
SMB_WOD
Write Operation Done
This bit is set by iMC when a SMBus Write command has been completed on the
SMBus. It is cleared by iMC when a subsequent SMBus Write command is issued.
29 RW-V 0h
SMB_SBE
SMBus Error
This bit is set by iMC if an SMBus transaction (including the TSOD polling or
message channel initiated SMBus access) that does not complete successfully
(non-Ack has been received from slave at expected Ack slot of the transfer). If a
slave device is asserting clock stretching, IMC does not have logic to detect this
condition to set the SBE bit directly; however, the SMBus master will detect the
error at the corresponding transaction’s expected ACK slot.
Note: Once the SMBUS_SBE bit is set, iMC stops issuing hardware-initiated TSOD
polling SMBUS transactions until the SMB_SBE is cleared. iMC will not increment
the SMB_STAT_x.TSOD_SA until the SMB_SBE is cleared. Manual SMBus
command interface is not affected; that is, new command issue will clear the
SMB_SBE