Datasheet

Datasheet, Volume 2 345
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Processor Uncore Configuration Registers
4.2.7.5 MH_CHN_ASTN—MEMHOT Domain Channel Association Register
MH_CHN_ASTN
Bus: 1 Device: 15 Function: 0 Offset: 11Ch
Bit Attr
Reset
Value
Description
31:24 RV 0h Reserved
23:20 RO Bh
MH1_2ND_CHN_ASTN
MemHot[1]# 2nd Channel Association bit 23 is valid bit.
Note: Valid bit means the association is valid and it does not imply the channel is
populated.
bit 22-20 = 2nd channel ID within this MEMHOT domain.
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
19:16 RO Ah
MH1_1ST_CHN_ASTN
MemHot[1]# 1st Channel Association bit 19 is valid bit.
Note: Valid bit means the association is valid and it does not implies the channel
is populated.
bit 18-16 = 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
15:8 RV 0h Reserved
7:4 RO 9h
MH0_2ND_CHN_ASTN
MemHot[0]# 2nd Channel Association bit 7 is valid bit.
Note: Valid bit means the association is valid and it does not implies the channel
is populated.
bit 6-4 = 2nd channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.
3:0 RO 8h
MH0_1ST_CHN_ASTN
MemHot[0]# 1st Channel Association bit 3 is valid bit.
Note: Valid bit means the association is valid and it does not implies the channel
is populated or exist.
bit 2-0 = 1st channel ID within this MEMHOT domain
Note: This register is hardcoded in design. It is read-accessible by firmware.
Design must make sure this register is not removed by downstream tools.