Datasheet
Processor Uncore Configuration Registers
344 Datasheet, Volume 2
4.2.7.4 MH_IO_500NS_CNTR—MEMHOT Input Output and 500ns
Counter Register
MH_IO_500NS_CNTR
Bus: 1 Device: 15 Function: 0 Offset: 118h
Bit Attr
Reset
Value
Description
31:22 RW-LV 000h
MH1_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH0_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1]# output driver may be turned on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
count is equal or less than MH_IN_SENSE_ASSERT, MEM_HOT[1:0]#, output is
disabled and receiver is turned on. Hardware will decrement this counter by 1
every time CNTR_500_NANOSEC is decremented to zero. When the counter is
zero, the next CNFG_500_NANOSEC count is loaded with MH_IN_SENSE_ASSERT.
This counter is subject to PMSI pause (at quiencense) and resume (at wipe).
21:12 RW-LV 000h
MH0_IO_CNTR
MEM_HOT[1:0]# Input Output Counter in number of CNTR_500_NANOSEC. When
MH_IO_CNTR is zero, the counter is loaded with MH_SENSE_PERIOD in the next
CNTR_500_NANOSEC. When count is greater than MH_IN_SENSE_ASSERT, the
MEM_HOT[1:0]# output driver may be turn on if the corresponding
MEM_HOT#event is asserted. The receiver is turned off during this time. When
count is equal or less than MH_IN_SENSE_ASSERT, MEM_HOT[1:0]# output is
disabled and receiver is turned on. BIOS calculates the number of
CNTR_500_NANOSEC (hardware will decrement this register by 1 every
CNTR_500_NANOSEC). When the counter is zero, the next CNTR_500_NANOSEC
count is loaded with MH_IN_SENSE_ASSERT. This counter is subject to PMSI
pause (at quiencense) and resume (at wipe).
11:10 RV 0h Reserved
9:0 RW-LV 000h
CNTR_500_NANOSEC
500 ns base counters used for the MEM_HOT counters and the SMBus counters.
BIOS calculates the number of DCLK to be equivalent to 500 nanoseconds.
CNTR_500_NANOSEC (hardware will decrement this register by 1 every
CNTR_500_NANOSEC). When the counter is zero, the next CNTR_500_NANOSEC
count is loaded with CNFG_500_NANOSEC. This counter is subject to PMSI pause
(at quiencense) and resume (at wipe).