Datasheet

Processor Uncore Configuration Registers
342 Datasheet, Volume 2
4.2.7 Integrated Memory Controller MemHot Registers
These registers Control for the Integrated Memory Controller thermal throttle logic for
each channel.
4.2.7.1 MH_MAINCNTL—MEMHOT Main Control Register
MH_MAINCNTL
Bus: 1 Device: 15 Function: 0 Offset: 104h
Bit Attr
Reset
Value
Description
31:19 RV 0h Reserved
18 RW 0h
MHOT_EXT_SMI_EN
Generate SMI event when either MEMHOT[1:0]# is externally asserted.
17 RW 0h
MHOT_SMI_EN
Generate SMI during internal MEMHOT# event assertion
16 RW 0b
Enabling external MEM_HOT sensing logic
Externally asserted MEM_HOTsense control enable bit.
When set, the MEM_HOT sense logic is enabled.
15 RW 1b
Enabling mem_hot output generation logic
MEM_HOT output generation logic enable control.
When 0, the MEM_HOT output generation logic is disabled (that is,
MEM_HOT[1:0]# outputs are in de-asserted state) no assertion regardless of the
memory temperature. Sensing of externally asserted MEM_HOT[1:0]# is not
affected by this bit. iMC will always reset the MH1_DIMM_VAL and
MH0_DIMM_VAL bits in the next DCLK so there is no impact to the PCODE update
to the MH_TEMP_STAT registers.
When 1, the MEM_HOT output generation logic is enabled.