Datasheet

Datasheet, Volume 2 341
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Processor Uncore Configuration Registers
4.2.6.6 RCOMP_TIMER—RCOMP Wait Timer Register
Defines the time from IO starting to run RCOMP evaluation until RCOMP results are
definitely ready. This counter is added in order to keep determinism of the process if
operated in different modes
The register also indicates that first RCOMP has been done - required by BIOS
RCOMP_TIMER
Bus: 1 Device: 15 Function: 0 Offset: C0h
Bit Attr
Reset
Value
Description
31 RW 0b
rcomp_in_progress
rcomp in progress status bit
30:22 RV 0h Reserved
21 RW 0b
ignore_mdll_locked_bit
Ignore DDRIO MDLL lock status during rcomp when set
20 RW 0b
no_mdll_fsm_override
Do not force DDRIO MDLL on during rcomp when set
19:17 RV 0h Reserved
16 RW-LV 0b
First RCOMP has been done in DDRIO
This is a status bit that indicates the first RCOMP has been completed. It is cleared
on reset, and set by MC hardware when the first RCOMP is completed. BIOS
should wait until this bit is set before executing any DDR command
Locked by the inverted output of MCMAIN.PSMI_QSC_CNTL.FORCERW
15:0 RW 044Ch
COUNT
DCLK cycle count that MC needs to wait from the point it has triggered RCOMP
evaluation until it can trigger the load to registers