Datasheet

Processor Uncore Configuration Registers
340 Datasheet, Volume 2
4.2.6.5 MC_INIT_STATE_G—Initialization State for Boot, Training 
and IOSAV Register
This register defines the high-level behavior in IOSAV mode. It defines the DDR reset
pin value, DCLK enable, refresh enable IOSAV synchronization features and bits
indicating the MRC status
This register is lock by uCR LT_IOSAV_MEMINIT_DIS
MC_INIT_STATE_G
Bus: 1 Device: 15 Function: 0 Offset: B4h
Bit Attr
Reset
Value
Description
31:13 RV 0h Reserved
12:9 RWS-L 0h
cs_oe_en
Per channel CS output enable override
8RWS-L1b
MC is in SR
This bit indicates if it is safe to keep the MC in SR during MC-reset. If it is clear
when reset occurs, it means that the reset is without warning and the DDR-reset
should be asserted. If set when reset occurs, it indicates that DDR is already in SR
and it can keep it this way. This bit can also indicate MRC if reset without warning
has occurred, and if it has, cold-reset flow should be selected.
7RW-L 0b
MRC_DONE
This bit indicates the PCU that the MRC is done, MC is in normal mode, ready to
serve, and PCU may begin power-control operations.
MRC should set this bit when MRC is done, but it doesn’t need to wait until training
results are saved in BIOS flas.h
5RW-L 1b
DDRIO Reset (internal logic): DDR IO reset (also known as TrainReset in
RTL)
To reset the I/O this bit has to be set for 20 DCLKs and then cleared. Setting this
bit will reset the DDRIO receive FIFO registers only.
It is required in some of the training steps
4RW-L 1b
IOSAV sequence channel sync
This bit is used to sync the IOSAV operation in four channels. It is expected that
BIOS clear the bit after IOSAV test. Clearing the bit during test may lead to
unknown behavior. By setting it four channels get the enable together
3RW-L 0b
Refresh Enable
If cold reset, this bit should be set by BIOS after:
1. Initializing the refresh timing parameters
2. Running DDR through reset and init sequence
If warm reset or S3 exit, this bit should be set immediately after SR exit
2RW-L 0b
DCLK Enable (for all channels)
DCLK Enable (for all channels)
1RW-L 1b
DDR_RESET
DDR reset for all DIMMs from all channels within this socket. No IMC/DDRIO logic
is reset by asserting this register.
This bit is negative logic! That is, writing 0 to induce a reset and write 1 for not
reset.