Datasheet

Configuration Process and Registers
34 Datasheet, Volume 2
• Device 16: Integrated Memory Controller Channel 0, 1, 2 and 3. Device 16,
Function 0, 1, 4 and 5 contains the Thermal control registers for Integrated
Memory Controller. Channel 0 resides at DID of 3CB4h. Channel 1 resides at DID of
3CB5h. Channel 2 resides at DID of 3CB0h. Channel 3 resides at DID of 3CB1h.
Device 16, Function 2, 3, 6 and 7 contains the test registers for the Integrated
Memory Controller.
• Device 19: Processor performance monitoring and Ring. Device 19, Function 1
contains the processor Ring to PCI Express performance monitoring registers and
resides a DID of 3C43h.
2.2 Configuration Register Rules
Types of registers:
• PCI Configuration Space Registers (CSRs)
• CSRs are chipset specific registers that are located at PCI defined address space.
2.2.1 CSR Access
Configuration space registers are accessed using the configuration transaction
mechanism defined in the PCI specification and this uses the bus:device:function
number concept to address a specific device’s configuration space. Accesses to PCI
configuration registers is achieved using NcCfgRd/Wr transactions on the Ring.
All configuration register accesses are accessed over Message Channel through the
UBox but might come from a variety of different sources:
•Local cores
•PECI or JTAG
This unit supports PCI configuration space access as defined in the PCI Express Base
Specification, Revision 3.0. Configuration registers can be read or written in Byte,
WORD (16-bit), or DWord (32-bit) quantities. Accesses larger than a DWord to PCI
Express configuration space will result in unexpected behavior. All multi-byte numeric
fields use “little-endian” ordering (that is, lower addresses contain the least significant
parts of the field).
2.2.2 PCI Bus Number
In the tables shown for IIO devices ( 0–7), the PCI Bus numbers are all marked as “Bus
0”.The specific bus number for all PCIe* devices in the processor is specified in the
CPUBUSNO register “CPUBUSNO—CPU Internal Bus Numbers Register” on page 165
which exists in the I/O module’s configuration space.
2.2.3 Uncore Bus Number
In the tables shown for Uncore devices (8 - 19), the PCI Bus numbers are all marked as
“bus 1”. The specific bus number for all PCIe devices in the processor is specified in the
CPUBUSNO register found at “CPUBUSNO—CPU Internal Bus Numbers Register” on
page 165.