Datasheet
Datasheet, Volume 2 339
Processor Uncore Configuration Registers
4.2.6.3 TADWAYNESS_[0:11]—TAD Range Wayness, Limit and
Target Register
There are total of 12 TAD ranges (N+P+1= number of TAD ranges; P= how many times
channel interleave changes within the SAD ranges.).
4.2.6.4 MCMTR2—MC Memory Technology Register 2
MC Memory Technology Register 2
TADWAYNESS_[0:11]
Bus: 1 Device: 15 Function: 0 Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h,
9Ch
Bus: 1 Device: 15 Function: 0 Offset: A0h, A4h, A8h, ACh
Bit Attr
Reset
Value
Description
31:12 RW-LB 00000h
TAD_LIMIT
highest address of the range in system address space, 64 MB granularity; that is,
TADRANGLIMIT[45:26].
11:10 RW-LB 0h
TAD_SKT_WAY
socket interleave wayness
00 = 1 way,
01 = 2 way,
10 = 4 way,
11 = 8 way.
9:8 RW-LB 0h
TAD_CH_WAY: Channel Interleave Wayness
00 = interleave across 1 channel
01 = interleave across 2 channels
10 = interleave across 3 channels
11 = interleave across 4 channels
Note: This parameter effectively tells iMC how much to divide the system address
by when adjusting for the channel interleave. Since both channels in a pair store
every line of data, divide by 1 when interleaving across one pair and 2 when
interleaving across two pairs. For HA, it tells how may channels to distribute the
read requests across. When interleaving across 1 pair, distribute the reads to two
channels; when interleaving across 2 pairs, distribute the reads across 4 pairs.
Writes always go to both channels in the pair when the read target is either
channel.
7:6 RW-LB 0h
TAD_CH_TGT3
Target channel for channel interleave 3 (used for 4-way TAD interleaving).
This register is used in the iMC only for reverse address translation for logging
spare/patrol errors, converting a rank address back to a system address.
5:4 RW-LB 0h
TAD_CH_TGT2
Target channel for channel interleave 2 (used for 3/4-way TAD interleaving).
3:2 RW-LB 0h
TAD_CH_TGT1
Target channel for channel interleave 1 (used for 2/3/4-way TAD interleaving).
1:0 RW-LB 0h
TAD_CH_TGT0
Target channel for channel interleave 0 (used for 1/2/3/4-way TAD interleaving).
MCMTR2
Bus: 1 Device: 15 Function: 0 Offset: B0h
Bit Attr
Reset
Value
Description
31:4 RV 0h Reserved
3:0 RW-L 0h
MONROE_CHN_FORCE_SR: Monroe Technology software channel force
SRcontrol.
When set, the corresponding channel is ignoring the ForceSRExit. A new
transaction arrive at this channel will still cause the SR exit.