Datasheet

Processor Uncore Configuration Registers
338 Datasheet, Volume 2
4.2.6.2 MCMTR—MC Memory Technology Register
MCMTR
Bus: 1 Device: 15 Function: 0 Offset: 7Ch
Bit Attr
Reset
Value
Description
31:10 RV 0h Reserved
8RW-LB0b
NORMAL
0 = IOSAV mode
1 = Normal Mode
7:4 RV 0h Reserved
3RW-LB0b
DIR_EN
Note: This bit will only work if the SKU is enabled for this feature.
Changing this bit will require BIOS to re-initialize the memory.
2RW-LB0h
ECC_EN: ECC Enable
Note: This bit will only work if the SKU is enabled for this feature
1RW-LB0h
LS_EN
Use lock-step channel mode if set; otherwise, independent channel mode.
Note: This bit will only work if the SKU is enabled for this feature
0RW-LB0h
CLOSE_PG
Use close page address mapping if set; otherwise, open page.