Datasheet

Datasheet, Volume 2 337
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Processor Uncore Configuration Registers
4.2.5.12 SAD_Control—SAD Control Register
4.2.6 Integrated Memory Controller Target Address Registers
This section describes the PCI/PCIe registers that are present in this unit. It covers
registers from offset 40h to FFh for PCI configuration space or 80h to FFFh for PCIe
configuration space.
The following Memory Controller Main Registers are part of the address decode
functions.
4.2.6.1 PXPCAP—PCI Express* Capability Register
SAD_Control
Bus: N Device: 13 Function: 6 Offset: F4h
Bit Attr
Reset
Value
Description
31:3 RV 0h Reserved
2:0 RW-L 0h
Local_NodeID
NodeID of the local Socket.
PXPCAP
Bus: 1 Device: 15 Function: 0 Offset: 40h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:25 RO 00h
Interrupt Message Number
Not applicable for this device
24 RO 0b
Slot Implemented
Not applicable for integrated endpoints
23:20 RO 9h
Device/Port Type
Device type is Root Complex Integrated Endpoint
19:16 RO 1h
Capability Version
PCI Express Capability is Compliant with Version 1.0 of the PCI Express
Specification.
Note: This capability structure is not compliant with Versions beyond 1.0, since
they require additional capability registers to be reserved. The only purpose for
this capability structure is to make enhanced configuration space available.
Minimizing the size of this structure is accomplished by reporting version 1.0
compliancy and reporting that this is an integrated root port device. As such, only
three DWords of configuration space are required for this structure.
15:8 RO 00h
Next Capability Pointer
Pointer to the next capability. Set to 0 to indicate there are no more capability
structures.
7:0 RO 10h
Capability ID
Provides the PCI Express capability ID assigned by PCI-SIG.