Datasheet

Processor Uncore Configuration Registers
336 Datasheet, Volume 2
4.2.5.10 IOAPIC_Target_LIST—IOAPIC Target List Register
4.2.5.11 SAD_Target—SAD Target List
IOAPIC_Target_LIST
Bus: N Device: 13 Function: 6 Offset: ECh
Bit Attr
Reset
Value
Description
31:24 RV 0h Reserved
23:21 RW-LB 0h
Package7
NodeID of the IOAPIC target.
20:18 RW-LB 0h
Package6
NodeID of the IOAPIC target.
17:15 RW-LB 0h
Package5
NodeID of the IOAPIC target.
14:12 RW-LB 0h
Package4
NodeID of the IOAPIC target.
11:9 RW-LB 0h
Package3
NodeID of the IOAPIC target.
8:6 RW-LB 0h
Package2
NodeID of the IOAPIC target.
5:3 RW-LB 0h
Package1
NodeID of the IOAPIC target.
2:0 RW-LB 0h
Package0
NodeID of the IOAPIC target.
SAD_Target
Bus: N Device: 13 Function: 6 Offset: F0h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
12 RW-LB 0b Enable SourceID Feature
11:9 RW-LB 000b
SourceID
SourceID of the Socket. Programmable by BIOS. By default, the value should be
part of the APICID that represent the socket.
8:6 RW-LB 0h
VGA_Target
Target NodeID of the VGA Target
5:3 RW-LB 0h
Legacy_PCH_Target
Target NodeID of the Legacy PCH Target
2:0 RW-LB 0h
Flash_Target
Target NodeID of the Flash Target