Datasheet

Processor Uncore Configuration Registers
332 Datasheet, Volume 2
4.2.5.3 TOLM—Top of Low Memory Register
4.2.5.4 TOHM—Top of High Memory Register
4.2.5.5 MMIO_RULE[0:7]—MMIO Rule 0 Register
11 RW 0h
DowngradeFtoS
Downgrade all F state to S state
10 RW 0h
MtoIBias
Use MtoI policy as opposed to MtoS policy
9RV0hReserved
8RW0b
DrdGOSonEM
Enable GOS on E/M state for DRD
7RW0h
DPSrcSnoop
Enable DP Early Snoop optimization
6:1 RV 0h Reserved
0RW0h
EGO
Enable Cbo Early GO mode
TOLM
Bus: 1 Device: 12 Function: 7 Offset: 80h
Bit Attr
Reset
Value
Description
31:4 RV 0h Reserved
3:0 RW-LB 1h
Top of low memory
This register contains bits 31 to 28 of an address one byte above the maximum
DRAM memory below 4G that is usable by the operating system.
TOHM
Bus: 1 Device: 12 Function: 7 Offset: 84h
Bit Attr
Reset
Value
Description
31:21 RV 0h Reserved
20:0 RW-LB 007FFFh
Top of High Memory
This register contains bits 45:25 of an address one byte above the maximum
DRAM memory; above 4 GB that is usable by the operating system.
MMIO_RULE[0:7]
Bus: N Device: 13 Function: 6 Offset: 80h, 88h, 90h, 98h, A0h, A8h, B0h,
B8h
Bit Attr
Reset
Value
Description
63:46 RV 0h Reserved
Cbo_Coh_Config
Bus: 1 Device: 12 Function: 7 Offset: 50h
Bit Attr
Reset
Value
Description