Datasheet
Processor Uncore Configuration Registers
330 Datasheet, Volume 2
4.2.4.24 DRAM_RULE_9—DRAM Rule 9 Register
4.2.4.25 INTERLEAVE_LIST_9—DRAM Interleave List 9 Register
DRAM_RULE_9
Bus: 1 Device: 12 Function: 6 Offset: C8h
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25:6 RW-LB 00000h
Limit
This field correspond to Addr[45:26] of the DRAM rule top limit address. Must be
strictly greater then previous rule, even if this rule is disabled, unless this rule and
all following rules are disabled. Lower limit is the previous rule (or 0 if this is the
first rule)
5:4 RV 0h Reserved
3:2 RW-LB 00b
Attribute for DRAM rule
00 = DRAM
01 = MMCFG
10 = NXM (not POR for the processor)
1RW-LB0h
Interleave_Mode
DRAM rule interleave mode. If a dram_rule hits a 3 bit number is used to index
into the corresponding interleave_list to determine which package the DRAM
belongs to. This mode selects how that number is computed.
1 = Address bits {8,7,6}.
0 = Address bits {8,7,6} XORed with {18,17,16}.
0RW-LB0h
RULE_ENABLE
Enable for this DRAM rule.
INTERLEAVE_LIST_9
Bus: 1 Device: 12 Function: 6 Offset: CCh
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:27 RW-LB 0h
Package7
NodeID of the Interleave List target.
26:24 RW-LB 0h
Package6
NodeID of the Interleave List target.
23:22 RV 0h Reserved
21:19 RW-LB 0h
Package5
NodeID of the Interleave List target.
18:16 RW-LB 0h
Package4
NodeID of the Interleave List target.
15:14 RV 0h Reserved
13:11 RW-LB 0h
Package3
NodeID of the Interleave List target.
10:8 RW-LB 0h
Package2
NodeID of the Interleave List target.
7:6 RV 0h Reserved
5:3 RW-LB 0h
Package1
NodeID of the Interleave List target.
2:0 RW-LB 0h
Package0
NodeID of the Interleave List target.