Datasheet

Configuration Process and Registers

32 Datasheet, Volume 2

also contains the extended PCI Express configuration space that include PCI

Express error status/control registers and Isochronous and Virtual Channel

controls.

• Device 2: PCI Express Root Port 2a, 2b, 2c and 2d. Logically this appears as a

“virtual” PCI-to-PCI bridge residing on PCI bus 0 and is compliant with PCI Express

Specification Revision 3.0. Device 2 contains the standard PCI Express/PCI

configuration registers including PCI Express Memory Address Mapping registers. It

also contains the extended PCI Express configuration space that include PCI

Express Link status/control registers and Isochronous and Virtual Channel controls.

• Device 3: PCI Express Root Port 3a, 3b, 3c and 3d. Logically this appears as a

“virtual” PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with PCI Express

Local Bus Specification Revision 3.0. Device 3 contains the standard PCI Express/

PCI configuration registers including PCI Express Memory Address Mapping

registers. It also contains the extended PCI Express configuration space that

include PCI Express error status/control registers and Isochronous and Virtual

Channel controls.

• Device 5: Integrated I/O Core. This device contains the Standard PCI registers for

each of its functions. This device implements three functions; Function 0 contains

Address Mapping, Intel

Virtualization Technology (Intel

VT) for Directed I/O

(Intel

VT-d) related registers and other system management registers. Function 4

contains System Control/Status registers and miscellaneous control/status

registers on power management and throttling.