Datasheet

Datasheet, Volume 2 319
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Processor Uncore Configuration Registers
4.2.4.3 SMRAMC—System Management RAM Control Register
SMRAMC
Bus: 1 Device: 12 Function: 6 Offset: 4Ch
Bit Attr
Reset
Value
Description
31:7 RV 0h Reserved
6RW-LB 0b
D_OPEN: SMM Space Open (D_OPEN)
When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made visible even when
SMM decode is not active. This is intended to help BIOS initialize SMM space.
Software should ensure that D_OPEN=1 and D_CLS=1 are note set at the same
time.
5RW-LB 0b
D_CLS: SMM Space Closed (D_CLS)
When D_CLS = 1 SMM space DRAM is not accessible to data references, even if
SMM decode is active. Code references may still access SMM space DRAM. This
will allow SMM software to reference through SMM space to update the display
even when SMM is mapped over the VGA range. Software should ensure that
D_OPEN=1 and D_CLS=1 are not set at the same time.
4RW-LB 0b
D_LCK
Processor note: The following described the original intention of D_LCK. In the
processor ES1, D_LCK set to 1 will make DRAM_RULEs and INTERLEAVE_LIST
read only. However, the plan is to fix this in ES2 where D_LCK will effectively have
no effect to any other registers.
<Stale D_LCK information, does not apply to the processor>
SMM Space Locked (D_LCK): When D_LCK is set to 1 then D_OPEN is reset to 0
and D_LCK, D_OPEN, C_BASE_SEG, G_SMRAME, PCIEXBAR, (DRAM_RULEs and
INTERLEAVE_LISTs) become read only. D_LCK can be set to 1 using a normal
configuration space write but can only be cleared by a Reset. The combination of
D_LCK and D_OPEN provide convenience with security. The BIOS can use the
D_OPEN function to initialize SMM space and then use D_LCK to ’lock down’ SMM
space in the future so that no application software (or BIOS itself) can violate the
integrity of SMM space, even if the program has knowledge of the D_OPEN
function.
3RW-LB 0b
G_SMRAM: Global SMRAM Enable (G_SMRAME)
If set to a 1, then Compatible SMRAM functions are enabled, providing 128 KB of
DRAM accessible at the A0000h address while in SMM (ADSB with SMM decode).
To enable Extended SMRAM function this bit has to be set to 1. Once D_LCK is set,
this bit becomes read only.
2:0 RO 010b
C_BASE_SEG: Compatible SMM Space Base Segment (C_BASE_SEG)
This field indicates the location of SMM space. SMM DRAM is not remapped. It is
simply made visible if the conditions are right to access SMM space; otherwise,
the access is forwarded to HI. Only SMM space between A0000h and BFFFFh is
supported so this field is hardwired to 010.