Datasheet

Datasheet, Volume 2 317
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Processor Uncore Configuration Registers
4.2.4.2 PAM456—CBO SAD PAM Register
9:8 RW 0h
PAM1_LOENABLE: 0C0000h-0C3FFFh Attribute (LOENABLE)
This field controls the steering of read and write cycles that address the BIOS area
from 0C0000h to 0C3FFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
7:6 RV 0h Reserved
5:4 RW-LB 0h
PAM0_HIENABLE: 0F0000h-0FFFFFh Attribute (HIENABLE)
This field controls the steering of read and write cycles that address the BIOS area
from 0F0000h to 0FFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
3:0 RV 0h Reserved
PAM456
Bus: 1 Device: 12 Function: 6 Offset: 44h
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21:20 RW 0h
PAM6_HIENABLE: 0EC000h-0EFFFFh Attribute (HIENABLE)
This field controls the steering of read and write cycles that address the BIOS area
from 0EC000h to 0EFFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
19:18 RV 0h Reserved
17:16 RW 0h
PAM6_LOENABLE: 0E8000h-0EBFFFh Attribute (LOENABLE)
This field controls the steering of read and write cycles that address the BIOS area
from 0E8000h to 0EBFFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
15:14 RV 0h Reserved
13:12 RW 0h
PAM5_HIENABLE: 0E4000h-0E7FFFh Attribute (HIENABLE)
This field controls the steering of read and write cycles that address the BIOS area
from 0E4000h to 0E7FFFh.
00 = DRAM Disabled: All accesses are directed to DMI.
01 = Read Only: All reads are sent to DRAM. All writes are forwarded to DMI.
10 = Write Only: All writes are send to DRAM. Reads are serviced by DMI.
11 = Normal DRAM Operation: All reads and writes are serviced by DRAM.
11:10 RV 0h Reserved
PAM0123
Bus: 1 Device: 12 Function: 6 Offset: 40h
Bit Attr
Reset
Value
Description