Datasheet

Datasheet, Volume 2 31
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Configuration Process and Registers
2 Configuration Process and
Registers
2.1 Platform Configuration Structure
The DMI2 physically connects the processor and the PCH. From a configuration
standpoint, the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices
in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software.
As a result, all devices internal to the processor and the PCH appear to be on PCI Bus 0.
2.1.1 Processor IIO Devices (CPUBUSNO (0))
The processor IIO contains 10 PCI devices within a single, physical component. The
configuration registers for the devices are mapped as devices residing on PCI Bus
“CPUBUSNO(0) ” where CPUBUSNO(0) is programmable by BIOS.
• Device 0: DMI2 Root Port. Logically this appears as a PCI device residing on PCI
Bus 0. Device 0 contains the standard PCI header registers, extended PCI
configuration registers and DMI2 device specific configuration registers.
• Device 1: PCI Express Root Port 1a and 1b. Logically this appears as a “virtual”
PCI-to-PCI bridge residing on PCI Bus 0 and is compliant with the PCI Express Local
Bus Specification Revision 3.0. Device 1 contains the standard PCI Express/PCI
configuration registers including PCI Express Memory Address Mapping registers. It
Figure 2-1. Processor Integrated I/O Device Map
Bus= CPUBUSNO(0)*
PCH
DMI2 Host
Bridge or PCIe
Root Port
(Device 0)
Integrated I /O Core
(Device 5)
Memory Map/VTd
(Function 0)
IOAPIC (Function 4)
PCIe Port 1a
(Dev#1, F#0)
PCIe Port 1b
(Dev#1, F#1)
IOU Port 1IOU Port 2IOU Port 3
PCIe Port 2a
(Dev#2, F#0)
PCIe Port 2b
(Dev#2, F#1)
PCIe Port 2c
(Dev#2, F#2)
PCIe Port 2d
(Dev#2, F#3)
PCIe Port 3a
(Dev#3, F#0)
PCIe Port 3b
(Dev#3, F#1)
PCIe Port 3c
(Dev#3, F#2)
PCIe Port 3d
(Dev#3, F#3)
Processor