Datasheet

Datasheet, Volume 2 305
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Processor Uncore Configuration Registers
4.2.3.10 CBO_GDXC_PKT_CNTRL—CBO GDXC Packet Control Register
This register is controlled by lock bit GDXCLCK in XXX register. The register may be
readable with the lock bit set but no writes will take effect unless the lock bit is set to 0.
CBO_GDXC_PKT_CNTRL
Bus: 1 Device: 12 Function: 0 CFG Mode: Parent
Offset: 80h
Bus: 1 Device: 12 Function: 0 Offset: 80h
Bus: 1 Device: 12 Function: 1 Offset: 80h
Bus: 1 Device: 12 Function: 2 Offset: 80h
Bus: 1 Device: 12 Function: 3 Offset: 80h
Bus: 1 Device: 13 Function: 0 Offset: 80h
Bus: 1 Device: 13 Function: 1 Offset: 80h
Bus: 1 Device: 13 Function: 2 Offset: 80h
Bus: 1 Device: 13 Function: 3 Offset: 80h
Bit Attr
Reset
Value
Description
31:16 RV 0h Reserved
7RV0hReserved
6RWS-L0h
CBo Dbg Bus Seq Match Disable
CBo Dbg Bus Seq Match Disable
5RWS-L0b
CBo GDXC Spare Control Bit #2
Spare bit for CBo GDXC Packet control
4RWS-L0b
CBo GDXC Spare Control Bit #1
Spare bit for CBo GDXC Packet control
3RWS-L0b
CBo GDXC the Processor Time Stamp
When asserted, the time stamp mechanism used with IDI messages is switched to
the Intel
®
Core™ i7 processor family for the LGA-2011 socket approach. The
message format is not otherwise affected.
2RWS-L0b
CBo GDXC PMA IDI Message Enable
The IDI-like message issued from the PMA (generally associated with certain
power management events) is enabled by this bit. When not asserted, the CBo
MCI arbiter will not receive any PMA IDI message valid signal.
1RWS-L0b
GDXC Time Stamp NOP Message Enable
GDXC ësyncí and ësuper syncí events result in a construction of a NOP with the
appropriate Time Stamp value. When this bit not asserted, the CBo MCI arbiter
will not receive any NOP message valid signal (effectively dropping this message).