Datasheet

Datasheet, Volume 2 303
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Processor Uncore Configuration Registers
4.2.3.5 VNA_Credit_Config—VNA Credit Configuration Register
Register related to VNA Credit Configuration
4.2.3.6 PipeRspFunc—Pipe Response Function Register
Pipe Response Function
VNA_Credit_Config
Bus: 1 Device: 12 Function: 0 CFG Mode: Parent
Offset: 54h
Bus: 1 Device: 12 Function: 0 Offset: 54h
Bus: 1 Device: 12 Function: 1 Offset: 54h
Bus: 1 Device: 12 Function: 2 Offset: 54h
Bus: 1 Device: 12 Function: 3 Offset: 54h
Bus: 1 Device: 13 Function: 0 Offset: 54h
Bus: 1 Device: 13 Function: 1 Offset: 54h
Bus: 1 Device: 13 Function: 2 Offset: 54h
Bus: 1 Device: 13 Function: 3 Offset: 54h
Bit Attr
Reset
Value
Description
31 RWS 0b
Cbo Coherency Configuration
Disable ISOC VN credit reservation
30 RWS 0b VNA Credit Change
29:15 RV 0h Reserved
14:12 RWS 010b
BL_VNA_R2PCIE
BL VNA credit count for R2PCIE (processor note, the VNA credit count toward
R2PCIE can’t exceed 3, so the maximum value should be 3 or less)
11:9 RWS 001b
BL_VNA_R3QPI1
BL VNA credit count for R3QPI1
8:6 RWS 001b
BL_VNA_R3QPI0
BL VNA credit count for R3QPI0
5:3 RWS 001b
AD_VNA_R3QPI1
AD VNA credit count for R3QPI1
2:0 RWS 001b
AD_VNA_R3QPI0
AD VNA credit count for R3QPI0
PipeRspFunc
Bus: 1 Device: 12 Function: 0 CFG Mode: Parent
Offset: 58h
Bus: 1 Device: 12 Function: 0 Offset: 58h
Bus: 1 Device: 12 Function: 1 Offset: 58h
Bus: 1 Device: 12 Function: 2 Offset: 58h
Bus: 1 Device: 12 Function: 3 Offset: 58h
Bus: 1 Device: 13 Function: 0 Offset: 58h
Bus: 1 Device: 13 Function: 1 Offset: 58h
Bus: 1 Device: 13 Function: 2 Offset: 58h
Bus: 1 Device: 13 Function: 3 Offset: 58h
Bit Attr
Reset
Value
Description
31:17 RV 0h Reserved
16:13 RWS 0000b Trigger Selection
12 RWS 0b Force Reject
11:2 RWS 000h Error Injection Mask
1RWS0bError Injection State Enable
0RWS0bErrInjCVEn