Datasheet
Datasheet, Volume 2 3
Contents
1Introduction............................................................................................................25
1.1 Document Terminology ......................................................................................25
1.2 Related Documents ...........................................................................................27
1.3 Register Terminology.........................................................................................28
2 Configuration Process and Registers .......................................................................31
2.1 Platform Configuration Structure .........................................................................31
2.1.1 Processor IIO Devices (CPUBUSNO (0)).....................................................31
2.1.2 Processor Uncore Devices (CPUBUSN0 (1))................................................33
2.2 Configuration Register Rules...............................................................................34
2.2.1 CSR Access ...........................................................................................34
2.2.2 PCI Bus Number.....................................................................................34
2.2.3 Uncore Bus Number................................................................................34
2.3 Configuration Mechanisms..................................................................................35
2.3.1 Standard PCI Express* Configuration Mechanism........................................35
2.4 Device Mapping.................................................................................................35
3 Processor Integrated I/O (IIO) Configuration Registers .........................................37
3.1 Processor IIO Devices (PCI Bus CPUBUSNO (0))....................................................37
3.2 PCI Configuration Space Registers (CSRs)......................................................37
3.2.1 Unimplemented Devices/Functions and Registers........................................37
3.2.2 PCI Bus Number.....................................................................................37
3.2.3 IIO PCI Express* Configuration Space Registers .........................................40
3.2.4 Standard PCI Configuration Space (Type 0/1
Common Configuration Space).................................................................47
3.2.4.1 VID—Vendor Identification Register.............................................47
3.2.4.2 DID—Device Identification Register .............................................47
3.2.4.3 PCICMD—PCI Command Register................................................48
3.2.4.4 PCISTS—PCI Status Register......................................................49
3.2.4.5 RID—Revision Identification Register...........................................51
3.2.4.6 CCR—Class Code Register..........................................................51
3.2.4.7 CLSR—Cacheline Size Register....................................................51
3.2.4.8 PLAT—Primary Latency Timer Register.........................................52
3.2.4.9 HDR—Header Type Register .......................................................52
3.2.4.10 HDR—Header Type Register .......................................................52
3.2.4.11 BIST—Built-In Self Test Register.................................................53
3.2.4.12 PBUS—Primary Bus Number Register...........................................53
3.2.4.13 SECBUS—Secondary Bus Number Register...................................53
3.2.4.14 SUBBUS—Subordinate Bus Number Register.................................53
3.2.4.15 IOBAS—I/O Base Register..........................................................54
3.2.4.16 IOLIM—I/O Limit Register ..........................................................54
3.2.4.17 SECSTS—Secondary Status Register ...........................................55
3.2.4.18 MBAS—Memory Base Register ....................................................56
3.2.4.19 MLIM—Memory Limit Register.....................................................56
3.2.4.20 PBAS—Prefetchable Memory Base Register...................................57
3.2.4.21 PLIM—Prefetchable Memory Limit Register ...................................57
3.2.4.22 PBASU—Prefetchable Memory Base (Upper 32 bits) Register........... 57
3.2.4.23 PLIMU—Prefetchable Memory Limit (Upper 32 bits) Register ........... 58
3.2.4.24 SVID—Subsystem Vendor ID Register..........................................58
3.2.4.25 SDID—Subsystem Identity.........................................................59
3.2.4.26 CAPPTR—Capability Pointer........................................................59
3.2.4.27 CAPPTR—Capability Pointer........................................................59
3.2.4.28 INTL—Interrupt Line Register .....................................................59
3.2.4.29 INTPIN—Interrupt Pin Register ...................................................60
3.2.4.30 BCTRL—Bridge Control Register..................................................60
3.2.4.31 SCAPID—Subsystem Capability Identity Register...........................61