Datasheet

Datasheet, Volume 2 297

Processor Uncore Configuration Registers
Table 4-15. Memory Controller Channel 2 DIMM Training Registers: Bus N, Device 16,
Function 0, Offset 400h–4FCh 
Memory Controller Channel 3 DIMM Training Registers: Bus N, Device 16,
Function 1, Offset 400h–4FCh
Memory Controller Channel 0 DIMM Training Registers: Bus N, Device 16,
Function 4, Offset 400h–4FCh
Memory Controller Channel 1 DIMM Training Registers: Bus N, Device 16,
Function 5, Offset 400h–4FCh
IOSAV_SPEC_CMD_ADDR_0 400h 480h
IOSAV_SPEC_CMD_ADDR_1 404h
484h
IOSAV_SPEC_CMD_ADDR_2 408h
488h
IOSAV_SPEC_CMD_ADDR_3 40Ch
48Ch
IOSAV_CH_ADDR_UPDT_0 410h
490h
IOSAV_CH_ADDR_UPDT_1 414h
494h
IOSAV_CH_ADDR_UPDT_2 418h
498h
IOSAV_CH_ADDR_UPDT_3 41Ch
49Ch
IOSAV_CH_ADDR_LFSR_0 420h
4A0h
IOSAV_CH_ADDR_LFSR_1 424h
4A4h
IOSAV_CH_ADDR_LFSR_2 428h
4A8h
IOSAV_CH_ADDR_LFSR_3 42Ch
4ACh
IOSAV_CH_SPCL_CMD_CTRL_0 430h
4B0h
IOSAV_CH_SPCL_CMD_CTRL_1 434h
4B4h
IOSAV_CH_SPCL_CMD_CTRL_2 438h
4B8h
IOSAV_CH_SPCL_CMD_CTRL_3 43Ch
4BCh
IOSAV_CH_SUBSEQ_CTRL_0 440h
4C0h
IOSAV_CH_SUBSEQ_CTRL_1 444h
4C4h
IOSAV_CH_SUBSEQ_CTRL_2 448h
4C8h
IOSAV_CH_SUBSEQ_CTRL_3 44Ch
4CCh
IOSAV_CH_SEQ_CTRL 450h
4D0h
IOSAV_CH_STAT 454h
4D4h
458h 4D8h
IOSAV_CH_DATA_CNTL 45Ch
4DCh
IOSAV_CH_DATA_CYC_MSK 460h
4E0h
464h 4E4h
468h 4E8h
46Ch 4ECh
470h 4F0h
474h 4F4h
478h 4F8h
47Ch 4FCh