Datasheet

Processor Uncore Configuration Registers
296 Datasheet, Volume 2
Table 4-14. Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,
Function 0, Offset 300h–3FCh 
Memory Controller Channel 3 DIMM Timing Registers: Bus N, Device 16,
Function 1, Offset 300h–3FCh
Memory Controller Channel 0 DIMM Timing Registers: Bus N, Device 16,
Function 4, Offset 300h–3FCh
Memory Controller Channel 1 DIMM Timing Registers: Bus N, Device 16,
Function 5, Offset 300h–3FCh
RSP_FUNC_MCCTRL_ERR_INJ 300h 380h
PWMM_STARV_CNTR_PRESCALER 304h
384h
WDBWM 308h
388h
WDAR_MODE 30Ch
38Ch
310h 390h
314h 394h
318h 398h
31Ch 39Ch
320h 3A0h
324h 3A4h
328h 3A8h
32Ch 3ACh
330h 3B0h
334h 3B4h
SPARING 338h
3B8h
33Ch 3BCh
340h 3C0h
344h 3C4h
348h 3C8h
34Ch 3CCh
350h 3D0h
354h 3D4h
358h 3D8h
35Ch 3DCh
360h 3E0h
364h 3E4h
368h 3E8h
36Ch 3ECh
370h 3F0h
374h 3F4h
378h 3F8h
37Ch 3FCh