Datasheet

Datasheet, Volume 2 295

Processor Uncore Configuration Registers
Table 4-13. Memory Controller Channel 2 DIMM Timing Registers: Bus N, Device 16,
Function 0, Offset 200h–2FCh 
Memory Controller Channel 3 DIMM Timing Registers: Bus N, Device 16,
Function 1, Offset 200h–2FCh
Memory Controller Channel 0 DIMM Timing Registers: Bus N, Device 16,
Function 4, Offset 200h–2FCh
Memory Controller Channel 1 DIMM Timing Registers: Bus N, Device 16,
Function 5, Offset 200h–2FCh
TCDBP 200h MC_INIT_STAT_C 280h
TCRAP 204h
284h
TCRWP 208h
288h
TCOTHP 20Ch
28Ch
TCRFP 210h
290h
TCRFTP 214h
294h
TCSRFTP 218h
298h
TCMR2SHADOW 21Ch
29Ch
TCZQCAL 220h
2A0h
TCSTAGGER_REF 224h
2A4h
228h 2A8h
TCMR0SHADOW 22Ch
2ACh
230h 2B0h
RPQAGE 234h
2B4h
IDLETIME 238h
2B8h
RDIMMTIMINGCNTL 23Ch
2BCh
RDIMMTIMINGCNTL2 240h
2C0h
TCMRS 244h
2C4h
248h 2C8h
24Ch 2CCh
250h 2D0h
254h 2D4h
258h 2D8h
25Ch 2DCh
RD_ODT_TBL0 260h
2E0h
RD_ODT_TBL1 264h
2E4h
RD_ODT_TBL2 268h
2E8h
26Ch 2ECh
WR_ODT_TBL0 270h
2F0h
WR_ODT_TBL1 274h
2F4h
WR_ODT_TBL2 278h
2F8h
27Ch 2FCh