Datasheet

Datasheet, Volume 2 293
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Processor Uncore Configuration Registers
Table 4-11. Memory Controller Channel 2 Thermal Control Registers: Bus N, Device 16,
Function 0, Offset 00h–FCh 
Memory Controller Channel 3 Thermal Control Registers: Bus N, Device 16,
Function 1, Offset 00h–FCh
Memory Controller Channel 0 Thermal Control Registers: Bus N, Device 16,
Function 4, Offset 00h–FCh
Memory Controller Channel 1 Thermal Control Registers: Bus N, Device 16,
Function 5, Offset 00h–FCh
DID VID 0h 80h
PCISTS PCICMD 4h
84h
CCR RID 8h
88h
BIST HDR PLAT CLSR Ch
8Ch
10h 90h
14h 94h
18h 98h
1Ch 9Ch
20h
PmonCntr_0
A0h
24h A4h
28h
PmonCntr_1
A8h
SDID SVID 2Ch ACh
30h
PmonCntr_2
B0h
CAPPTR 34h B4h
38h
PmonCntr_3
B8h
MAXLAT MINGNT INTPIN INTL 3Ch BCh
PXPCAP 40h
PmonCntr_4
C0h
44h C4h
48h
PmonDbgCntResetVal
C8h
4Ch CCh
50h
PmonCntr_Fixed
D0h
54h D4h
58h PmonCntrCfg_0 D8h
5Ch PmonCntrCfg_1 DCh
60h PmonCntrCfg_2 E0h
64h PmonCntrCfg_3 E4h
68h PmonCntrCfg_4 E8h
6Ch PmonDbgCtrl ECh
70h F0h
74h PmonUnitCtrl F4h
78h PmonUnitStatus F8h
7Ch FCh