Datasheet

Datasheet, Volume 2 289
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Processor Uncore Configuration Registers
Table 4-7. Memory Controller RAS Registers: Bus N, Device 15, Function 1, 
Offset 00h–FCh
DID VID 0h SPAREADDRESSLO 80h
PCISTS PCICMD 4h
84h
CCR RID 8h
88h
BIST HDR PLAT CLSR Ch
8Ch
10h 90h
14h SSRSTATUS 94h
18h SCRUBADDRESSLO 98h
1Ch SCRUBADDRESSHI 9Ch
20h SCRUBCTL A0h
24h A4h
28h SPAREINTERVAL A8h
SDID SVID 2Ch RASENABLES ACh
30h B0h
CAPPTR 34h B4h
38h LEAKY_BUCKET_CFG B8h
MAXLAT MINGNT INTPIN INTL 3Ch
BCh
PXPCAP 40h LEAKY_BUCKET_CNTR_LO C0h
44h LEAKY_BUCKET_CNTR_HI C4h
48h C8h
4Ch CCh
50h MTCTL D0h
54h MAXMTR D4h
58h MTLFSR D8h
5Ch MTLFSRSEED DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
7Ch FCh