Datasheet

Processor Uncore Configuration Registers
288 Datasheet, Volume 2
Table 4-6. Memory Controller MemHot and SMBus Registers: Bus N, Device 15, 
Function 0, Offset 100h–1FCh
100h SMB_STAT_0 180h
MH_MAINCNTL 104h SMBCMD_0 184h
108h SMBCntl_0 188h
MH_SENSE_500NS_CFG 10Ch SMB_TSOD_POLL_RATE_CNTR_0 18Ch
MH_DTYCYC_MIN_ASRT_CNTR_0 110h SMB_STAT_1 190h
MH_DTYCYC_MIN_ASRT_CNTR_1 114h SMBCMD_1 194h
MH_IO_500NS_CNTR 118h SMBCntl_1 198h
MH_CHN_ASTN 11Ch SMB_TSOD_POLL_RATE_CNTR_1 19Ch
MH_TEMP_STAT 120h SMB_PERIOD_CFG 1A0h
MH_EXT_STAT 124h SMB_PERIOD_CNTR 1A4h
128h SMB_TSOD_POLL_RATE 1A8h
12Ch 1ACh
130h 1B0h
134h 1B4h
138h 1B8h
13Ch 1BCh
140h 1C0h
144h 1C4h
148h 1C8h
14Ch 1CCh
150h 1D0h
154h 1D4h
158h 1D8h
15Ch 1DCh
160h 1E0h
164h 1E4h
168h 1E8h
16Ch 1ECh
170h 1F0h
174h 1F4h
178h 1F8h
17Ch 1FCh