Datasheet

Datasheet, Volume 2 287
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Processor Uncore Configuration Registers
Table 4-5. Memory Controller Target Address Decoder Registers: Device 15, 
Function 0, Offset 00h–FCh
DID VID 0h TADWAYNESS_0 80h
PCISTS PCICMD 4h TADWAYNESS_1 84h
CCR RID 8h TADWAYNESS_2 88h
BIST HDR PLAT CLSR Ch TADWAYNESS_3 8Ch
10h TADWAYNESS_4 90h
14h TADWAYNESS_5 94h
18h TADWAYNESS_6 98h
1Ch TADWAYNESS_7 9Ch
20h TADWAYNESS_8 A0h
24h TADWAYNESS_9 A4h
28h TADWAYNESS_10 A8h
SDID SVID 2Ch TADWAYNESS_11 ACh
30h MCMTR2 B0h
CAPPTR 34h MC_INIT_STATE_G B4h
38h B8h
MAXLAT MINGNT INTPIN INTL 3Ch
BCh
PXPCAP 40h RCOMP_TIMER C0h
44h C4h
48h C8h
4Ch CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
70h F0h
74h F4h
78h F8h
MCMTR 7Ch
FCh