Datasheet

Processor Uncore Configuration Registers
284 Datasheet, Volume 2
Table 4-2. System Address Decoder (CBo) : Device 12, Function 6, Offset 00h–FCh
DID VID 0h DRAM_RULE 80h
PCISTS PCICMD 4h INTERLEAVE_LIST 84h
CCR RID 8h DRAM_RULE_1 88h
BIST HDR PLAT CLSR Ch INTERLEAVE_LIST_1 8Ch
10h DRAM_RULE_2 90h
14h INTERLEAVE_LIST_2 94h
18h DRAM_RULE_3 98h
1Ch INTERLEAVE_LIST_3 9Ch
20h DRAM_RULE_4 A0h
24h INTERLEAVE_LIST_4 A4h
28h DRAM_RULE_5 A8h
SDID SVID 2Ch INTERLEAVE_LIST_5 ACh
30h DRAM_RULE_6 B0h
CAPPTR 34h INTERLEAVE_LIST_6 B4h
38h DRAM_RULE_7 B8h
MAXLAT MINGNT INTPIN INTL 3Ch INTERLEAVE_LIST_7 BCh
PAM0123 40h DRAM_RULE_8 C0h
PAM456 44h INTERLEAVE_LIST_8 C4h
48h DRAM_RULE_9 C8h
SMRAMC 4Ch INTERLEAVE_LIST_9 CCh
50h D0h
54h D4h
58h D8h
5Ch DCh
60h E0h
64h E4h
68h E8h
6Ch ECh
MESEG_BASE
70h
F0h
74h
F4h
MESEG_LIMIT
78h
F8h
7Ch
FCh