Datasheet

Datasheet, Volume 2 283
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Processor Uncore Configuration Registers
4.2 Integrated Memory Controller Configuration
Registers
The Integrated Memory Controller unit contains four controllers. Up to four channels
can be operated independently. The DRAM controllers share a common address
decode. Configuration registers may be per channel or common.
4.2.1 Processor Registers
All Integrated Memory Controller registers listed below are specific to the the processor.
4.2.2 CSR Register Maps
The following register maps are for Memory Controller control logic registers:
Table 4-1. Unicast CSR’s(CBo) : Device 12–13, Function 0–3, Offset 00h–FCh
DID VID 0h CBO_GDXC_PKT_CNTRL 80h
PCISTS PCICMD 4h
84h
CCR RID 8h
88h
BIST HDR PLAT CLSR Ch
8Ch
10h 90h
14h 94h
18h 98h
1Ch 9Ch
20h RTID_Config_Pool01_Base A0h
24h RTID_Config_Pool23_Base A4h
28h RTID_Config_Pool45_Base A8h
SDID SVID 2Ch RTID_Config_Pool67_Base ACh
30h RTID_Pool_Config B0h
CAPPTR 34h B4h
38h B8h
MAXLAT MINGNT INTPIN INTL 3Ch
BCh
RTID_Config_Pool01_Size 40h RTID_Config_Pool01_Base_Shadow C0h
RTID_Config_Pool23_Size 44h RTID_Config_Pool23_Base_Shadow C4h
RTID_Config_Pool45_Size 48h RTID_Config_Pool45_Base_Shadow C8h
RTID_Config_Pool67_Size 4Ch RTID_Config_Pool67_Base_Shadow CCh
50h RTID_Pool_Config_Shadow D0h
VNA_Credit_Config 54h
D4h
PipeRspFunc 58h
D8h
PipeDbgBusSel 5Ch
DCh
60h E0h
64h E4h
68h E8h
SadDbgMm2 6Ch
ECh
Cbsads_Unicast_Cfg_Spare 70h
F0h
74h F4h
78h F8h
7Ch FCh