Datasheet

Processor Uncore Configuration Registers
280 Datasheet, Volume 2
4.1.5 RID—Revision Identification Register
4.1.6 CCR—Class Code Register
4.1.7 CLSR—Cacheline Size Register
4.1.8 PLAT—Primary Latency Timer Register
RID
Offset: 8h
Bit Attr
Reset
Value
Description
7:0 RO 00h
Revision_ID
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in
any processor function.
Implementation Note: Read and write requests from the host to any RID
register in any processor function are re-directed to the IIO cluster. Accesses to
the CCR field are also redirected due to DWord alignment. It is possible that JTAG
accesses are direct, so will not always be redirected.
CCR
Offset: 9h
Bit Attr
Reset
Value
Description
23:16 RO 08h Base Class
Generic Device
15:8 RO 80h Sub-Class
Generic Device
7:0 RO 00h Register-Level Programming Interface
Set to 00h for all non-APIC devices.
CLSR
Offset: Ch
Bit Attr
Reset
Value
Description
7:0 RW 0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for
processor is always 64B.
PLAT
Offset: Dh
Bit Attr
Reset
Value
Description
7:0 RO 0h
Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.